发明名称 Methods and apparatus for managing page crossing instructions with different cacheability
摘要 An instruction in an instruction cache line having a first portion that is cacheable, a second portion that is from a page that is non-cacheable, and crosses a cache line is prevented from executing from the instruction cache. An attribute associated with the non-cacheable second portion is tracked separately from the attributes of the rest of the instructions in the cache line. If the page crossing instruction is reached for execution, the page crossing instruction and instructions following are flushed and a non-cacheable request is made to memory for at least the second portion. Once the second portion is received, the whole page crossing instruction is reconstructed from the first portion saved in the previous fetch group. The page crossing instruction or portion thereof is returned with the proper attribute for a non-cached fetched instruction and the reconstructed instruction can be executed without being cached.
申请公布号 US8819342(B2) 申请公布日期 2014.08.26
申请号 US201213626916 申请日期 2012.09.26
申请人 QUALCOMM Incorporated 发明人 DeBruyne Leslie Mark;Dieffenderfer James Norris;Mcilvaine Michael Scott;Stempel Brian Michael
分类号 G06F12/08;G06F9/38 主分类号 G06F12/08
代理机构 代理人 Kamarchik Peter Michael;Pauley Nicholas J.;Agusta Joseph
主权项 1. A method for managing page crossing instructions with different cacheability, the method comprising: setting an indication for an ending portion of an instruction that was fetched from a first page of non-cacheable instructions and established with a beginning portion of the instruction that was fetched from a second page of cacheable instructions in a cache line having cacheable instructions, wherein the instruction crosses a cache line boundary; detecting the indication in a fetch pipeline when hitting on the established cache line to set a non-cacheable flag to indicate that the instruction cannot be executed from the instruction cache, wherein the instruction is received but not executed from the cache based on the non-cacheable flag; and refetching at least the ending portion of the instruction from memory bypassing the cache in response to the non-cacheable flag to combine with the beginning portion of the instruction, wherein the instruction is reconstructed for execution.
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