Frequency synthesis with gapper

摘要

Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

主权项

1. An integrated circuit for frequency synthesis, said integrated circuit comprising:
a gapper configured to generate a first gapped signal based on an input signal; a first frequency divider coupled with said gapper and configured to receive said first gapped signal and generate a second gapped signal; and a phase locked loop (PLL) configured to receive said second gapped signal and generate an output signal, wherein, if a frequency ratio of said input signal to said output signal is less than 1, said gapper is configured to incorporate an factor that is greater than 1 from said first frequency divider.