发明名称 |
Method and apparatus for simulating gate capacitance of a tucked transistor device |
摘要 |
A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode is provided. The method includes receiving a first netlist having an entry for the tucked transistor device in a computing apparatus. The entry defines parameters associated with the gate electrode and the diffusion region. A parasitic capacitance component is added to the entry representing a gate capacitance between the floating gate and the diffusion region in the computing apparatus. |
申请公布号 |
US8818785(B2) |
申请公布日期 |
2014.08.26 |
申请号 |
US201113288541 |
申请日期 |
2011.11.03 |
申请人 |
GLOBALFOUNDRIES Inc.;Advanced Micro Devices, Inc. |
发明人 |
Goo Jung-Suk;Thuruthiyil Ciby;Ramasubramanian Venkat;Faricelli John |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
Amerson Law Firm, PLLC |
代理人 |
Amerson Law Firm, PLLC |
主权项 |
1. A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode, comprising:
receiving a first netlist having an entry for the tucked transistor device in a computing apparatus, the entry defining parameters associated with the gate electrode and the diffusion region; and adding a parasitic capacitance component to the entry in the computing apparatus, the parasitic capacitance component representing a gate capacitance between the floating gate and the diffusion region, wherein adding the parasitic capacitance component comprises generating a first value for the parasitic capacitance component based on a first capacitance of the floating gate electrode present in an initial portion of an operating range of the tucked transistor device and generating a second value for the parasitic capacitance component based on a capacitance of the floating gate electrode present in an inversion region of an operating range of the tucked transistor device; generating the first netlist based on the first value; generating a second netlist based on the second value; simulating operation of the tucked transistor device using a transistor device model and the first netlist to generate a first simulation result; and simulating operation of the tucked transistor device using the transistor device model and the second netlist to generate a second simulation result. |
地址 |
Grand Cayman KY |