| 摘要 |
Capacitive transducer systems are disclosed that reduce nonlinearities due to feedthrough capacitances or residual electrostatic forces. The systems can include a core with a first input coupled to a first variable capacitor, a second input coupled to a second variable capacitor, and a core output coupled to a common node; an amplifier with input switchably coupled to common node and an output; a feedback path switchably coupling amplifier output to common node; and a main clock with first and second phases, that controls switches coupling system components. When clock is in first phase, first core input is coupled to reference voltage, second core input is coupled to negative reference voltage, and common node is coupled to amplifier output. When clock is in second phase, core inputs are grounded, and common node is coupled to amplifier input. The system can have single amplifier. Neutralization capacitor can cancel feedthrough and parasitic capacitances. |
| 主权项 |
1. A differential capacitive transducer system that senses a physical quantity, the differential capacitive transducer system comprising:
a first capacitive core generating a first core output based on the physical quantity, the first capacitive core including a first variable capacitor, a second variable capacitor, a first core input coupled to the first variable capacitor, a second core input coupled to the second variable capacitor, and a first core output coupled to a first common node between the first variable capacitor and the second variable capacitor; a second capacitive core generating a second core output based on the physical quantity, the second capacitive core including a third variable capacitor, a fourth variable capacitor, a third core input coupled to the third variable capacitor, a fourth core input coupled to the fourth variable capacitor, and a second core output coupled to a second common node between the third variable capacitor and the fourth variable capacitor;a differential amplifier having a pair of differential inputs and a pair of differential outputs, differential inputs being switchably coupled to the first and second common nodes for receiving the first and second core outputs, the differential outputs providing the transducer output;
a first feedback path switchably coupling the transducer output to the first common node of the first capacitive core; a second feedback path switchably coupling the transducer output to the second common node of the second capacitive core; a main clock having a first phase and a second phase, the main clock controlling the opening and closing of switches coupling components of the capacitive transducer system; wherein when the main clock is in the first phase, the first input of the first capacitive core is coupled to a positive reference voltage, the second input of the first capacitive core is coupled to a negative reference voltage, the first common node of the first capacitive core is coupled to the transducer output, the third input of the second capacitive core is coupled to a positive reference voltage, the fourth input of the second capacitive core is coupled to a negative reference voltage, the second common node of the second capacitive core is coupled to the inverted transducer output, the negative reference voltage having substantially the same magnitude and opposite polarity as the positive reference voltage; and wherein when the main clock is in the second phase, the first, second, third and fourth inputs of the capacitive core are coupled to a common mode voltage, and the common nodes of the first and second capacitive cores are coupled to the differential inputs of the differential amplifier. |
