Method and apparatus for aligning and integrating serial data streams

摘要

An integrated circuit is incorporated into a communications system to enable a channel to achieve data rates that are at least double that which are currently achievable. The integrated circuit combines serial data signals using recovered clock and serial data signals in reference and non-reference clock domains. The integrated circuit rate converts recovered serial data in one of the clock domains, performs a phase alignment at the converted data rate, and returns the rate converted and phase-aligned serial data to the recovered data rate in response to the recovered clock from the remaining clock domain. Thereafter, the recovered and aligned serial data signals are combined. The phase alignment is monitored in circuitry that detects when a threshold offset is violated. When the threshold offset is violated a synchronization circuit is enabled.

主权项

1. A method for combining serial data streams, the method comprising:
in an interface having N input terminals and N/2 output terminals, receiving N serial data signals having a first data rate, wherein N is an even integer; recovering a first serial data signal received at a first of the N input terminals to generate a first clock signal operating at the first data rate in a first clock domain; dividing the first clock signal to generate a second clock signal operating at a second data rate in the first clock domain; applying a first set of recovered data signals at respective inputs of a first 2×1 multiplexer to generate a representation of the first serial data signal; recovering a second serial data signal received at a second of the N input terminals to generate a third clock signal operating at the first data rate in a second clock domain; dividing the third clock signal to generate a fourth clock signal operating at the second data rate in the second clock domain; applying a second set of recovered data signals at respective inputs of a 1×M demultiplexer operating in accordance with the fourth clock signal to generate a first representation of the second serial data signal, where M is an even integer; applying the first representation of the second serial data signal at an input of a 1×M multiplexer operating in accordance with the second clock signal to generate a second representation of the second serial data signal; and applying the representation of the first serial data signal and the second representation of the second serial data signal to the inputs of a second 2×1 multiplexer operating in accordance with the first clock signal to generate a combined serial data signal.