| 主权项 |
1. A clock state independent (CSI) state retention power gated (SRPG) cell, comprising:
an input control circuit that receives an input signal, wherein the input control circuit comprises a plurality of transistors configured as a first inverter transmission gate, and at least one transistor serially connected to the plurality of transistors that is controlled by at least one power gating signal, wherein the input control circuit comprises first and second P-channel transistors, and first, second and third N-channel transistors, wherein the second P-channel transistor, the first P-channel transistor, the first N-channel transistor, the second N-channel transistor and the third N-channel transistor are sequentially series connected; a first latch having an input coupled to an output of the input control circuit; a transmission gate having an input coupled to an output of the first latch, wherein an output of the transmission gate comprises at least one output of the SRPG cell; a second latch having an input coupled to the output of the transmission gate, wherein an output of the second latch comprises at least one output of the SRPG cell; and a second inverter transmission gate having an input coupled to the output of the second latch and an output coupled to the first latch. |
