| 摘要 |
Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by an adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal. |
| 主权项 |
1. A dynamic random access memory, comprising:
a memory array; a read/write circuit coupled to the memory array and configured to read data from and write data to the memory array; a buffer coupled to the read/write circuit and configured to be clocked according to an output clock signal; and a clock generator circuit coupled to the buffer and configured to provide the output clock signal, the clock generator circuit comprising:
a forward path configured to delay an input clock signal based, at least in part, on a delay clock signal to provide an output clock signal; anda feedback path coupled to the forward path and configured to provide the delay clock signal based, at least in part, on the output clock signal at a first frequency, the feedback path further configured to provide a duty cycle correction control signal based, at least in part, on the output clock signal at a second frequency, to adjust a duty cycle of a clock signal of the forward path according to the duty cycle correction control signal. |
