Electrical signal isolation and linearity in SOI structures

摘要

Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.

主权项

1. A structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of said structure, said structure comprising:
a trench extending through said top semiconductor layer and into a base oxide layer below said top semiconductor layer, wherein an oxide liner is formed on a top portion of said trench; a handle wafer situated below said base oxide layer; a void in said handle wafer disposed below said trench, said void improving electrical signal isolation between said adjacent devices situated in said top semiconductor layer.