Process charging protection for split gate charge trapping flash

摘要

A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.

主权项

1. A semiconductor device, comprising:
a plurality of memory cells in a substrate, each of the memory cells comprising:
a first gate disposed over a first dielectric,a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, anda first doped region in the substrate adjacent to the first gate and a second doped region in the substrate adjacent to the second gate; one or more p-n junctions formed within the substrate and electrically isolated from the first and second doped regions of each memory cell in the plurality of memory cells; a metal trace of a first metal layer extending along a single plane between a first via to the second gate of at least one memory cell in the plurality of memory cells, and a second via to a p-n junction within the one or more p-n junctions; and metal trace of a second metal layer extending along a plane between a third via to the first metal layer and a fourth via to the first metal layer.