Multi-trapping layer flash memory cell

摘要

A semiconductor device includes a semiconductor substrate, a top gate over the semiconductor substrate, and a stacked gate between the top gate and the semiconductor substrate. The stacked gate includes a first tunneling layer, a first storage layer adjoining the first tunneling layer, and an additional layer adjoining the first tunneling layer. The additional layer is selected from the group consisting of a retention layer and an additional composite layer. The additional composite layer comprises a second tunneling layer and a second storage layer adjoining the second tunneling layer. The semiconductor device further includes a blocking layer adjoining the first storage layer.

主权项

1. A semiconductor device comprising:
a semiconductor substrate; a top gate over the semiconductor substrate; a stacked gate between the top gate and the semiconductor substrate, wherein the stacked gate comprises:
a first tunneling layer having a first band gap;a first storage layer adjoining the first tunneling layer, the first storage layer having a second band gap smaller than the first band gap; andan additional layer adjoining the first tunneling layer, wherein the additional layer comprises a second storage layer adjacent the first tunneling layer and a second tunneling layer, the second storage layer having a third band gap and the second tunneling layer having a fourth band gap, the fourth band gap being smaller than the first band gap, the third band gap being smaller than the fourth band gap; a blocking layer adjoining and contacting the first storage layer, the blocking layer having a fifth band gap larger than the first band gap, wherein the first and the second tunneling layers each comprises SiO2 and an additional material selected from the group consisting essentially of silicon, nitrogen, and combinations thereof, and wherein the first tunneling layer has a lower additional material concentration than does the second tunneling layer; and a retention layer between the additional layer and the semiconductor substrate, the retention layer having a sixth band gap, the sixth band gap being larger than the fourth band gap.