Programming method for multi-level cell flash for minimizing inter-cell interference

摘要

Systems, methods and computer program products for minimizing floating gate coupling interference and threshold voltage drift associated with flash memory cells are described. In some implementations, the memory cells can be programmed in a predetermined sequence that allows pages with the most-significant bit (MSB) and central significant bit (CSB) to be programmed first prior to programming pages with the least-significant bit (LSB). This sequence allows neighboring cells (e.g., cells neighboring a target cell) to be programmed first so as to reduce the floating gate coupling interference and threshold voltage drift on the target cell that is to be programmed in the subsequent stage. To accommodate the programming sequence (e.g., at the device level), additional buffer memories can be added.

主权项

1. A memory controller configured to:
program first bit data into a first storage element of a memory cell array; program corresponding first bit data into one or more neighboring storage elements of the memory cell array after the first bit data has been programmed into the first storage element; and program last bit data into the first storage element after the corresponding first bit data has been programmed into the one or more neighboring storage elements.