Readout circuit for non-volatile memory device

摘要

Provided is a readout circuit for a non-volatile memory device, which has a large readout margin for distinguishing between 0 and 1 of data and has a small circuit area. A voltage output from a single bias circuit is applied to a gate of a memory element and a gate of an NMOS transistor serving as a reference current source to be compared with a current flowing through the memory element. Thus, the gates are controlled by the same voltage, and hence characteristics fluctuations in the operating temperature range and the operating power supply voltage range are reduced. Therefore, a large readout margin for distinguishing 0 and 1 of data can be obtained, resulting in a simplified circuit configuration.

主权项

1. A readout circuit for an electrically rewritable non-volatile memory device, comprising:
a memory element including a source connected to a ground voltage, and a gate connected to one end of a first memory element selection switch controlled by a first memory element selection control signal; a select gate transistor including a source connected to a drain of the memory element, and a gate controlled by a select gate selection control signal; a second memory element selection switch including one end connected to a drain of the select gate transistor, and another end connected to an output of the readout circuit, the second memory element selection switch being controlled by a second memory element selection control signal; a first NMOS transistor serving as a reference current source to be compared with a current flowing through the memory element; a current mirror circuit comprising a first PMOS transistor and a second PMOS transistor, the first PMOS transistor including a gate and a drain which are connected to a drain of the first NMOS transistor, the second PMOS transistor including a gate connected to the gate of the first PMOS transistor and a drain connected to the output of the readout circuit; and a first bias circuit including an output terminal connected to a gate of the first NMOS transistor and to another end of the first memory element selection switch.