| 发明名称 |
Contact structure and method for variable impedance memory element |
| 摘要 |
A memory element can include an opening formed within at least one insulating layer formed on an etch stop layer that exposes a first electrode portion and the etch stop layer at a bottom of the opening; a second electrode portion, formed on at least a side surface of the opening and in contact with the first electrode portion, the second electrode portion not filling the opening and being substantially not formed over a top surface of the at least one insulating layer; and at least one memory layer formed on a top surface of the at least one insulating layer and in contact with the second electrode portion, the at least one memory layer being reversibly programmable between at least two impedance states. Methods of forming such memory elements are also disclosed. |
| 申请公布号 |
US8816314(B2) |
申请公布日期 |
2014.08.26 |
| 申请号 |
US201213470286 |
申请日期 |
2012.05.12 |
| 申请人 |
Adesto Technologies Corporation |
发明人 |
Gopalan Chakravarthy |
| 分类号 |
H01L29/02 |
主分类号 |
H01L29/02 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory element, comprising:
an opening formed within at least one insulating layer formed on an etch stop layer that exposes a first electrode portion and the etch stop layer at a bottom of the opening; a second electrode portion, formed on at least a side surface of the opening and not formed over a top surface of the at least one insulating layer, the second electrode portion being in contact with the first electrode portion; and at least one memory layer formed on a top surface of the at least one insulating layer and in contact with the second electrode portion, the at least one memory layer being reversibly programmable between at least two impedance states; wherein the opening has no steps in its bottom surface for a low topography profile. |
| 地址 |
Sunnyvale CA US |
