TEST ARCHITECTURE HAVING MULTIPLE FPGA BASED HARDWARE ACCELERATOR BLOCKS FOR TESTING MULTIPLE DUTS INDEPENDENTLY

摘要

Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.

主权项

1. An automated test equipment (ATE) apparatus comprising:
a computer system comprising a system controller, said system controller communicatively coupled to a tester processor, wherein said system controller is operable to transmit instructions to said tester processor, and wherein said tester processor is operable to generate commands and data from said instructions for coordinating testing of a plurality of devices under test (DUTs); a plurality of FPGA components communicatively coupled to said tester processor via a bus, wherein each of said plurality of FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from said tester processor for testing a DUT of a plurality of DUTs; and a plurality of I/O ports, each for communicating with a respective DUT and each communicatively coupled to a respective FPGA of said plurality of FPGAs, and wherein said tester processor is configured to operate in one of a plurality of functional modes, said plurality of functional modes configured to allocate functionality for generating commands and data between said tester processor and said plurality of FPGA components.