ONE-CACHEABLE MULTI-CORE ARCHITECTURE

摘要

Technologies are generally described for methods, systems, and devices effective to implement one-cacheable multi-core architectures. In one example, a multi-core processor that includes a first and second tile may be configured to implement a one-cacheable architecture. The second tile may be configured to generate a request for a data block. The first tile may be configured to receive the request for the data block, and determine that the requested data block is part of a group of data blocks identified as one-cacheable. The first tile may further determine that the requested data block is stored in a first cache in the first tile. The first tile may send the data block from the first cache in the first tile to the second tile, and invalidate the data blocks of the group of data blocks in the first cache in the first tile.

主权项

1. A method for processing a request for a data block in a multi-core processor, the method comprising:
receiving the request for the data block at a first tile that includes a first core and a first cache, wherein the request is received from a second tile that includes a second core; determining, by the first tile, that the data block is part of a group of data blocks; determining, by the first tile, that one or more data blocks of the group are stored in the first cache in the first tile; sending, by the first tile, the data block from the first cache in the first tile to the second tile; and invalidating, by the first tile, the data block sent from the first tile to the second tile and each data block in the one or more data blocks of the group of data blocks that are stored in the first cache in the first tile.