| 摘要 |
PROBLEM TO BE SOLVED: To shorten a time before data and clock timings are locked in a half-rate CDR circuit.SOLUTION: A phase comparison circuit compares the phases of a data signal and a regeneration clock, and a charge pump circuit and a loop filter control a control voltage according to the output of the phase comparison circuit. A voltage control oscillation circuit generates two sine-wave clocks having a frequency corresponding to the control voltage and differing in phase by 90 degrees. A clock selector selects and outputs, as a regeneration clock, a sine-wave clock having a large voltage difference with respect to the center of amplitude at transition of the data signal, so that it is possible to select, as a regeneration clock, one of the two since-wave clocks which is closer to a phase to be locked, and to achieve swift convergence into a locked state. |
