发明名称 ADAPTIVE MULTILEVEL BINNING TO IMPROVE HIERARCHICAL CACHING
摘要 A device driver calculates a tile size for a plurality of cache memories in a cache hierarchy. The device driver calculates a storage capacity of a first cache memory. The device driver calculates a first tile size based on the storage capacity of the first cache memory and one or more additional characteristics. The device driver calculates a storage capacity of a second cache memory. The device driver calculates a second tile size based on the storage capacity of the second cache memory and one or more additional characteristics, where the second tile size is different than the first tile size. The device driver transmits the second tile size to a second coalescing binning unit. One advantage of the disclosed techniques is that data locality and cache memory hit rates are improved where tile size is optimized for each cache level in the cache hierarchy.
申请公布号 US2014237187(A1) 申请公布日期 2014.08.21
申请号 US201313772160 申请日期 2013.02.20
申请人 NVIDIA CORPORATION 发明人 DIMITROV Rouslan;BASTOS Rui;HAKURA Ziyad S.;LUM Eric B.
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项 1. A method for calculating a tile size for a plurality of cache memories in a cache hierarchy, the method comprising: calculating a storage capacity of a first cache memory; calculating a first tile size based on the storage capacity of the first cache memory and one or more characteristics of data being processed in a first portion of a graphics processing pipeline; transmitting the first tile size to a first coalescing binning unit; calculating a storage capacity of a second cache memory; calculating a second tile size based on the storage capacity of the second cache memory and one or more characteristics of data being processed in a second portion of the graphics processing pipeline, wherein the second tile size is different than the first tile size; transmitting the second tile size to a second coalescing binning unit.
地址 Santa Clara CA US