MAP DECODER HAVING LOW LATENCY AND OPERATION METHOD OF THE SAME

摘要

Provided is a maximum a posteriori (MAP) decoder having a low latency and an operation method of the MAP decoder, including a branch metric calculation block to calculate a branch metric based on a received signal, a processor control block to demultiplex a received signal in a certain trellis section, an Extrinsec vector, and the calculated branch metric value, and a processor to calculate a path metric entering each state node in a certain trellis section, compensate for the calculated path metric, and calculate a state metric to be applied to a next trellis section based on the compensated path metric.

主权项

1. A maximum a posteriori (MAP) decoder, comprising:
a branch metric calculation block to calculate a branch metric based on a received signal; a processor control block to demultiplex a received signal in a certain trellis section, an Extrinsec vector, and a value of the calculated branch metric; and a processor to calculate a path metric entering each state node in the certain trellis section based on an arbitrary recursive calculation, compensate for the calculated path metric, and calculate a state metric to be applied to a next trellis section based on the compensated the path metric.