PACKET PROCESSING WITH REDUCED LATENCY

摘要

Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

主权项

1. A driver circuit for reduced latency processing, said driver circuit comprising:
a network stack circuit configured to:
transition from an idle state to a polling state in response to receiving an interrupt from a network interface;process data from a data queue associated with said network interface, said processing in response to obtaining a queue lock associated with said data queue; andenable interrupts on said network interface, and return to said idle state in response to determining absence of a yield on said queue lock; and a queue lock circuit configured to:
provide said queue lock to a first requesting entity if said queue lock is available, wherein said requesting entity comprises said driver circuit and one or more user context processing modules;record said yield on said queue lock if said queue lock is unavailable in response to a request from a second requesting entity; andset said network stack circuit to said polling state in response to a release of said queue lock by said first requesting entity and the recording of said yield on said queue lock.