| 摘要 |
A row decoding circuit including row decoding blocks is provided. Each of the row decoding blocks includes row decoders. Each of the row decoders receives a pre-charge signal, and includes an inverter, a selecting transistor and at least one switch transistors. The inverter receives the corresponding pre-charge signal, and outputs a first control signal. The first source/drain of the selecting transistor is coupled to a system high voltage, the gate receives the first control signal, and the second source/drain outputs a corresponding row selecting signal to a memory array of a memory device. The switch transistors are coupled between the second source/drain of the selecting transistor and a corresponding first reference signal in series. When the selecting transistor is controlled by the first control signal and turned on, the first reference signal is set to a high voltage level. |
| 主权项 |
1. A row decoding circuit, applicable to a memory device, comprising:
a plurality of row decoding blocks, each of the row decoding blocks comprising a plurality of row decoders, and each of the row decoders comprising:
a selecting transistor, having a first source/drain coupled to a system high voltage, a gate receiving a first control signal and a second source/drain outputting a corresponding row selecting signal to a memory array of the memory device; andat least one switch transistors, coupled in series between the second source/drain of the selecting transistor and a corresponding first reference signal, and each of the switch transistors having a gate receiving a corresponding second control signal,wherein when the selecting transistor is controlled by the first control signal and turned on, the first reference signal is set to a high voltage level. |
