发明名称 SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
摘要 A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge. The command decoder is configured to output, in a test mode, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge.
申请公布号 US2014233334(A1) 申请公布日期 2014.08.21
申请号 US201414263262 申请日期 2014.04.28
申请人 Elpida Memory, Inc. 发明人 MATSUNAGA Kinu;AKAMATSU Hiroshi
分类号 G11C7/12;G11C7/22 主分类号 G11C7/12
代理机构 代理人
主权项 1. A device comprising: a command decoder configured to output, in a first operation mode, a first signal in response to a first transition edge of a first type of transition edge of a synchronous signal, and a second signal in response to a second transition edge of the first type of transition edge of the synchronous signal, wherein the first transition edge and the second transition edge are consecutive; wherein the command decoder is configured to output, in a second operation mode, the first signal in response to a third transition edge of a second type of transition edge of the synchronous signal different from the first type of transition edge, and the second signal in response to a fourth transition edge of the first type of transition edge of the synchronous signal, and wherein the third transition edge and the fourth transition edge are consecutive.
地址 Tokyo JP