SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

摘要

A high voltage/power semiconductor device using a low voltage logic well is provided. The semiconductor device includes a substrate, a first well region formed by being doped in a first location on a surface of the substrate, a second well region formed by being doped with impurity different from the first well region's in a second location on a surface of the substrate, an overlapping region between the first well region and the second well region where the first well region and the second well region substantially coexist, a gate insulating layer formed on the surface of the first and the second well regions and the surface of the overlapping region, a gate electrode formed on the gate insulating layer, a source region formed on an upper portion of the first well region, and a drain region formed on an upper portion of the second well region. The semiconductor device may also include a separating unit, which is formed in the second well region on the drain side and may be formed as a shallow trench isolation (STI) region having a lower depth than the second well region.

主权项

1. A semiconductor device, comprising:
a substrate; a first well region formed by being doped in a first location on a surface of the substrate; a second well region formed by being doped in a different type from the first well region in a second location on a surface of the substrate; an overlapping region between the first well region and the second well region where the first well region and the second well region substantially coexist; a gate insulating layer formed on a surface of the first and the second well regions and on a surface of the overlapping region; a gate electrode formed on the insulating layer; a source region formed on an upper portion of the first well region; and a drain region formed on an upper portion of the second well region, wherein a net doping concentration in the overlapping region gradually decreases from a boundary between the first well region and the overlapping region to a boundary between the second well region and the overlapping region, and a ratio of a length of the first well region overlapping the gate electrode to a length of the gate electrode ranges between 80% and 96%.