POSITIVE EDGE RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH

摘要

In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

主权项

1. A flip-flop circuit comprising:
a multiplexer configured to receive a first data bit, a scan data bit, a scan enable control signal and a binary logical compliment signal of the scan enable control signal, wherein the scan enable control signal and the binary logical compliment signal of the scan enable control signal determine whether a data output of the multiplexer is the binary compliment of the first data bit or the binary compliment of scan data bit; a master latch configured to receive the data output of the multiplexer, a clock signal, a binary logical compliment signal of the clock signal, a retain control signal and a binary logical compliment signal of the retain control signal, a reset signal and a binary logical compliment signal of the reset signal wherein the clock signal, the binary logical compliment signal of the clock signal, the retain control signal the binary logical compliment signal of the retain control signal, the reset signal and the binary logical compliment signal of the reset signal determine when the binary logical value of the data output of the multiplexer is presented on the output of the master latch and when the output of the master latch is latched in the mater latch; a transfer gate wherein the transfer gate transfers data from the output of the master latch to the output of the transfer gate when the clock signal transitions from a low logical value to a logical high value; a slave latch configured to receive the output of the transfer gate, a second data bit. the clock signal, the binary logical compliment signal of the clock signal, the retain control signal, the binary logical compliment signal of the retain control signal, a slave control signal and a binary logical compliment signal of the slave control signal wherein the clock signal, the binary logical compliment signal of the clock signal, the retain control signal, the binary logical compliment signal of the retain control signal, the slave control signal and the binary logical compliment signal of the slave control signal determine whether the output of the transfer gate or the second data bit (D2) is latched in the slave latch.