发明名称 Vertical Cavity Surface Emitting Laser With An Integrated Protection Diode
摘要 A semiconductor device includes a vertical cavity surface emitting laser (VCSEL) with an integrated protection diode arranged between the VCSEL and an emitting surface. By locating the protection diode above the VCSEL, a minimal increase in substrate area is consumed to protect the VCSEL from electrostatic discharge events. A relatively small capacitance introduced by the protection diode, is controllably adjusted by one of the radial size of the protection diode and the thickness of the intrinsic layer therein. The relatively small capacitance introduced by the protection diode enables the VCSEL to operate at data rates above 10 Gb/s.
申请公布号 US2014233595(A1) 申请公布日期 2014.08.21
申请号 US201313768780 申请日期 2013.02.15
申请人 AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. 发明人 Murty Ramana
分类号 H01S5/026;H01L33/60 主分类号 H01S5/026
代理机构 代理人
主权项 1. A semiconductor device comprising: a substrate having at least one layer of semiconductor material formed on an upper surface thereof; a vertical cavity surface emitting laser disposed on the upper surface of the at least one layer of semiconductor material, the vertical cavity surface emitting laser having a first distributed Bragg reflector formed in a first set of layers, wherein at least one of the first set of layers is of an n-type material, a cavity containing a light-emitting material disposed on top of the first plurality of layers, a second distributed Bragg reflector formed in a second set of layers, and a first p++ layer disposed on the second set of layers, wherein at least one of the second set of layers is of a p-type material, the vertical cavity surface emitting laser having an oxide layer proximal to the intrinsic layer arranged in the second set of layers, the oxide layer defining an aperture; a protection diode for protecting the vertical cavity surface emitting laser from electrostatic discharge events disposed on the first p++ layer located above the aperture, the protection diode having at least one layer of n-type semiconductor material disposed on the first p++ layer, an intrinsic layer disposed on the at least one layer of n-type semiconductor material, and a second p++ layer disposed on the intrinsic layer; an ohmic p-type contact pad and an ohmic n-type contact pad in contact with the vertical cavity surface emitting laser and protection diode; a first metal interconnect connecting the p-contact pad of the vertical cavity surface emitting laser with the n-contact of the protection diode; and a second metal interconnect connecting the n-contact pad of the vertical cavity surface emitting laser with the p-contact of the protection diode.
地址 Singapore SG