Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response

摘要

Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.

主权项

1. A method of operating a pipeline, the method comprising:
initiating execution of a first instruction in parallel with a second instruction in a processor, wherein the first instruction is a one cycle execution instruction and the second instruction is a two cycle execution instruction; receiving a notification of an interrupt in the processor before completing the execution of the first instruction and before completing the execution of the second instruction; completing the execution of the first instruction and saving a first execution result in a target register specified by the first instruction; completing the execution of the second instruction and saving a second execution result in an interrupt forwarding register in response to the notification without saving the second execution result in a target register specified by the second instruction; and restoring the second execution result from the interrupt forwarding register to the target register specified by the second instruction on a return from interrupt.