发明名称 |
Method of Semiconductor Integrated Circuit Fabrication |
摘要 |
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features. |
申请公布号 |
US2014235050(A1) |
申请公布日期 |
2014.08.21 |
申请号 |
US201414266069 |
申请日期 |
2014.04.30 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Yeh Ching-Fu;Lee Hsiang-Huan;Peng Chao-Hsian;Wu Hsien-Chang |
分类号 |
H01L21/768 |
主分类号 |
H01L21/768 |
代理机构 |
|
代理人 |
|
主权项 |
1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:
providing a substrate; depositing a conductive layer on the substrate; forming a patterned hard mask on the conductive layer; forming a catalyst layer on the conductive layer in a vertical interconnection region; growing a plurality of carbon nanotubes (CNTs) from the catalyst layer; and p1 etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features. |
地址 |
Hsin-Chu TW |