发明名称 |
APPARATUS FOR HIGH SPEED ROM CELLS |
摘要 |
A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line. The ROM cell further comprises a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line. |
申请公布号 |
US2014231921(A1) |
申请公布日期 |
2014.08.21 |
申请号 |
US201414263634 |
申请日期 |
2014.04.28 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Liaw Jhon-Jhy |
分类号 |
H01L27/112;H01L29/78 |
主分类号 |
H01L27/112 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus comprising:
a first first-level contact formed on a first active region of a transistor of a memory cell; a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line; and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line; a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line; and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line. |
地址 |
Hsin-Chu TW |