发明名称 Efficient parallel sub-packet decoding using multiple decoders, controller and task instructions
摘要 <p>A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders. Decoders are instructed to decode specific sub-packets by receiving task instructions including information identifying sub-packets and including an End-Of-Packet (EOP) or End-Of-Group (EOG) marker bit.</p>
申请公布号 EP2512056(B1) 申请公布日期 2014.08.20
申请号 EP20120005069 申请日期 2009.03.10
申请人 QUALCOMM INCORPORATED 发明人 ZANOTELLI, JOSEPH V.;NATH, MRINAL M.;CHAUDHURI, ARUNAVA;GHOSH, KAUSHIK;CHALLA, RAGHU N.;JING, WEIHONG
分类号 H04L1/00;G06F9/38;H03M13/00;H03M13/29;H03M13/41 主分类号 H04L1/00
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