Partitioning designs to facilitate certification

摘要

This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion. The method further includes providing the configuration settings for the second portion for programming into a PLD.

主权项

1. A method comprising:
generating, by one or more computer systems, a hardware description language (HDL) implementation of a circuit design to be implemented on a programmable logic device (PLD); partitioning, by the one or more computer systems, the circuit design into a first portion and a second portion, the first portion including an interface for coupling the first portion and the second portion; generating, by the one or more computer systems, a first programming file based on the HDL implementation that contains first configuration programming bits for only the first portion and that contains default programming bits for the second portion; generating, by the one or more computer systems, a second programming file based on the HDL implementation that contains second configuration programming bits for only the second portion and that contains default programming bits for the first portion; verifying, or providing to a third-party certification body for verification, at least the second configuration programming bits; revising the first portion; generating revised first configuration programming bits for the revised first portion; merging the revised first configuration programming bits for the revised first portion with the verified second configuration programming bits for the second portion; and providing the merged configuration programming bits for programming into a PLD.