Semiconductor memory device

摘要

In a semiconductor memory device in which each memory cell is constituted by one transistor, in a memory cell pattern, two adjacent bits form one diffusion pattern, two adjacent transistors share a source region, and two drain regions are separated from each other. A plurality of arrays in each of which at least a column of the diffusion patterns is disposed include bit lines, and the bit lines of the first array are independent of the bit lines of the second array. In an interface between the arrays, ends at one side of the bit lines of each of the arrays are located on an associated one of two drain regions which are separated from each other with the source region which is shared on one diffusion pattern sandwiched therebetween. This configuration can provide a sufficient bit-line separation width, and reduce the area.

主权项

1. A semiconductor memory device comprising:
a column of a plurality of cell patterns; a first bit line; and a second bit line, wherein: each of the plurality of cell patterns includes only one pair of transistors as a memory cell transistor, the one pair of transistors sharing a source region, two drain regions of the one pair of transistors being separated from each other, the plurality of cell patterns includes a first cell pattern comprising a first pair of transistors of a first transistor and a second transistor, the first bit line overlapping a first drain region of the first transistor and the second bit line overlapping a second drain region of the second transistor, the first bit line and the second bit line are separated from each other, and a first edge of the first bit line overlaps the first cell pattern and a second edge of the second bit line overlaps the first cell pattern, in a plan view.