| 发明名称 | Counter architecture for online DVFS profitability estimation | ||
| 摘要 | A counter architecture and a corresponding method are provided for estimating a profitability value of DVFS for a unit of work running on a computing device. The counter architecture and the corresponding method are arranged for dividing total execution time for executing a unit of work on the computing device into a pipelined fraction subject to clock frequency and a non-pipelined fraction due to off-chip memory accesses, and for estimating the DVFS profitability value from the pipelined and the non-pipelined fraction. | ||
| 申请公布号 | US8812808(B2) | 申请公布日期 | 2014.08.19 |
| 申请号 | US201013516850 | 申请日期 | 2010.12.10 |
| 申请人 | Universiteit Gent | 发明人 | Eyerman Stijn;Eeckhout Lieven |
| 分类号 | G06F12/00 | 主分类号 | G06F12/00 |
| 代理机构 | Bacon & Thomas, PLLC | 代理人 | Bacon & Thomas, PLLC |
| 主权项 | 1. A counter architecture for estimating a profitability value of dynamic voltage and frequency scaling (DVFS) for a unit of work running on a computing device, the counter architecture comprising: a computing unit configured to determine from a total execution time for executing the unit of work on the computing device at arbitrary frequency a pipelined fraction and a non-pipelined fraction due to off-chip memory accesses, and a decision unit that estimates the DVFS profitability value from these two fractions, wherein the computing unit and decision unit comprise hardware. | ||
| 地址 | Ghent BE | ||