Optimized design verification of an electronic circuit

摘要

A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also includes extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the design of the electronic circuit. Further, the method includes executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.

主权项

1. A method comprising:
reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof; abstracting, through the processor, partitions of the electronic circuit based on at least one functionality thereof as part of the verification of the design; grouping, through the processor, circuit elements of the electronic circuit under each partition based on at least one of type and size thereof as part of the verification; extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the circuit elements of the electronic circuit in the design; and executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.