Hardware WCK2CK training engine using meta-EDC sweeping and adjustably accurate voting algorithm for clock phase detection

摘要

One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.

主权项

1. A method for determining whether a clock signal internal to a memory component should be inverted, the method comprising:
programming a first clock generator with a particular clock phase; receiving, from each of at least two memory components, in response to a command clock signal transmitted by the first clock generator and a first write clock signal also transmitted by the first clock generator and having the particular clock phase, a phase advertisement indicating whether the first write clock signal is early, late, or transient relative to the command clock signal; computing a vote value based on the phase advertisements received from the at least two memory components; updating a vote tally based on the computed vote value; and determining, based on the vote tally, whether to invert either a second clock signal internal to a first of the at least two memory components or a third clock signal internal to a second of the at least two memory components.