发明名称 Receiving circuit, clock recovery circuit, and communication system
摘要 High data-rate magnetic coupling communication is realized with a small circuit size without sacrificing the communication distance.;A received data acquisition circuit performs a decision-feedback equalization process on a received signal to obtain a shaped signal, and also performs sampling of the shaped signal with a sampling rate equal to or higher than a self-resonant frequency, according to a sampling clock, to obtain a data sample. A midpoint sample acquisition circuit performs sampling of the received signal at an intermediate timing of a sampling timing of the received data acquisition circuit to obtain a midpoint sample. A phase adjustment circuit adjusts a phase of the sampling clock, based on the data sample and the midpoint sample.
申请公布号 US8811556(B2) 申请公布日期 2014.08.19
申请号 US201313892090 申请日期 2013.05.10
申请人 Renesas Electronics Corporation 发明人 Yamaguchi Kouichi
分类号 H04L7/00;H04L25/40 主分类号 H04L7/00
代理机构 McGinn IP Law Group, PLLC 代理人 McGinn IP Law Group, PLLC
主权项 1. A receiving circuit which receives, via a transmission path formed by magnetic coupling of inductors at a transmission side and a receiving side, a signal corresponding to transmission data having a data rate equal to or higher than a self-resonant frequency of the inductors, the receiving circuit comprising: a received data acquisition circuit which performs a decision-feedback equalization process on the received signal to obtain a shaped signal and, according to a sampling clock, performs sampling of the shaped signal with a same sampling rate as the data rate to obtain data samples; and a clock recovery circuit which corrects the sampling clock so that the received data acquisition circuit performs sampling at a correct sampling timing, wherein the clock recovery circuit includes: a midpoint sample acquisition circuit which performs sampling of the received signal at an intermediate timing of the sampling timing of the received data acquisition circuit to obtain a midpoint sample; and a phase adjustment circuit which adjusts a phase of the sampling clock, based on the data samples and the midpoint sample.
地址 Kawasaki-shi, Kanagawa JP