Power reduction circuit and method

摘要

A method of reducing leakage current in a memory circuit is disclosed (FIG. 8A). The method includes connecting a first supply voltage terminal (VDD) to a bulk terminal of a transistor in an active mode of operation. The method further includes detecting a low power mode (SLEEP) of operation of the transistor and disconnecting the first supply voltage terminal from the bulk terminal in response to the step of detecting.

主权项

1. A method of reducing leakage current in a memory circuit, comprising:
connecting a first supply voltage terminal to a bulk terminal of a first transistor of the memory circuit in an active mode of operation; applying a high level of a control signal to at least one terminal of a memory cell of the memory circuit; detecting a first low power mode of operation of the memory circuit; and disconnecting the first supply voltage terminal from the bulk terminal during the step of applying and floating the bulk terminal in response to the step of detecting.