Memory device and memory control unit

摘要

A memory device is configured to generate a signal having a temperature compensation function. The device includes a mode register configured to store error detection and correction (EDC) mode data, and an EDC pattern generator configured to receive pattern information and period information included in the mode data and to generate an EDC pattern signal based on the pattern information and the period information. The EDC pattern signal is a periodic signal obtained by repeating a signal pattern based on the pattern information at a periodic rate corresponding to a signal period based on the period information. In some cases, the EDC pattern signal may be disabled during a portion of the signal period.

主权项

1. A device, comprising:
a mode register configured to store an error detection and correction (EDC) mode data, including pattern information and period information for an EDC pattern; and an EDC pattern generator configured to receive the pattern information and the period information and to generate the EDC pattern signal based on the pattern information and the period information, wherein the EDC pattern signal is a periodic signal comprising a series of signal periods based on the period information, wherein at least one signal period includes an active period and a hold period, wherein the EDC pattern signal includes in the active period a signal pattern based on the pattern information, and wherein the EDC pattern signal is in a disabled state during the hold period, wherein the pattern information comprises a first EDC pattern signal parameter including first EDC pattern signal parameter bits, wherein the signal pattern is obtained by repeating the first EDC pattern signal parameter bits during the active period, and wherein the EDC pattern generator comprises:
a synthesizer configured to receive the first EDC pattern signal parameter bits and to output the first EDC pattern signal; anda control signal generator configured to output a periodic operation signal to the synthesizer wherein a period of the operation signal is based on the period information.