Clock and data recovery circuitry with auto-speed negotiation and other possible features

摘要

An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).

主权项

1. An integrated circuit comprising:
clock and data recovery (“CDR”) circuitry for operating on an input serial data signal to recover data information from the input signal and for outputting the recovered data information in a retimed data signal, the CDR circuitry including a first circuit element that is controllable by a first control signal to perform in any of a plurality of different ways, and a plurality of circuitry for scaling frequency of signals; and utilization circuitry for monitoring the retimed data signal in order to detect a communication change request in the retimed data signal and for changing the first control signal in response to detection of such a communication change request, wherein the first circuit element is controllable by the first control signal to operate at any of a continuous range of frequencies, and wherein the utilization circuitry controls each of the plurality of circuitry for scaling frequency of signals.