| 摘要 |
Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections. |
| 主权项 |
1. A method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit, said method comprising:
accessing, by the CAD system, a first trace pattern for first metal traces on a first metal layer; accessing, by the CAD system, a second trace pattern for second metal traces on a second metal layer, vertically adjacent to said first metal layer; accessing, by the CAD system, a first via pattern of intended via interconnections between said first and second metal traces; and forming, by the CAD system, a second via pattern based on the first via pattern, the second via pattern indicating a plurality of areas in which vias are allowed during manufacturing of the integrated circuit, the areas of the second via pattern being larger than and enclosing the intended via interconnections of the first via pattern. |
