Methods of anneal after deposition of gate layers

摘要

Multi-stage preheat high-temperature anneal processes after the deposition of the gate dielectric layer(s) reduce the number of interfacial sites and improve the negative bias temperature instability (NTBI) performance of a p-type metal-oxide-semiconductor transistor (PMOS). The gate dielectric layers may include an interfacial oxide layer and a high-k dielectric layer. The multi-stage preheat is designed to reduce dopant deactivation and to improve inter-mixing between the interfacial oxide layer and the high-k dielectric layer. The high-temperature anneal is used to reduce the number of interfacial sites at the interface between the silicon substrate and the interfacial oxide layer.

主权项

1. A method of fabricating a gate structure of a p-type metal-oxide-semiconductor transistor (PMOS) device on a silicon substrate, comprising:
forming the gate structure on the substrate, wherein the gate structure includes an opening after one or more dummy layers have been removed to form the opening; forming an interfacial oxide layer on the silicon substrate in the opening; depositing a high dielectric constant (high-k) dielectric layer over the interfacial oxide layer; and performing a 2-stage preheat high-temperature anneal to reduce a number of interfacial sites at an interface between the silicon substrate and the interfacial oxide layer and to improve the PMOS negative bias temperature instability (NTBI) performance of the PMOS device, wherein a first stage preheat is performed at a temperature in a range from about 400° C. to about 600° C., and wherein a second stage preheat is performed at a temperature in a range from about 700° C. to about 900° C., and a high temperature anneal is performed at a peak temperature in a range from 875° C. to about 1200° C.