PHASE-FREQUENCY DECECTOR PROVING FREQUENCY MULTIPLYING, PHASE LOCKED LOOP COMPRISING THE PHASE-FREQUENCY DECECTOR, AND CLOCK AND DATA RECOVERY CIRCUIT COMPRISING THE PHASE-FREQUENCY DECECTOR

摘要

PURPOSE: A phase frequency detector supplying a frequency multiplication function, a phase-locked loop and a data recovery circuit including the phase frequency detector are provided to reduce a jitter of an internal clock signal or a jitter of a time-controlled data signal. CONSTITUTION: A phase frequency detector(600) includes a first flip-flop(610), a second flip-flop(620), a third flip-flop(630), an n-th flip-flop(640) and a reset unit(650). The first flip-flop outputs an up-signal being set as a second logic if a specific edge of a first clock signal is inputted. The second flip-flop or the n-th flip-flop is serially connected and outputs a down-signal being set as the second logic if a specific edge of a second clock signal is inputted. The reset unit resets each n flip-flop so that the up-signal or down-signal is to be a first logic if the up-signal or down-signal is the second logic.