发明名称 INTERCONNECTION STRUCTURE FOR AN INTEGRATED CIRCUIT
摘要 The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.
申请公布号 US2014225278(A1) 申请公布日期 2014.08.14
申请号 US201414257543 申请日期 2014.04.21
申请人 STMicroelectronics (Crolles 2) SAS 发明人 Vannier Patrick
分类号 H01L23/522 主分类号 H01L23/522
代理机构 代理人
主权项 1. An integrated circuit comprising: a first conductive element embedded within a first dielectric layer and having an exposed upper surface; a first etch stop layer located directly on a first portion of the exposed upper surface of the first conductive element and directly on the first dielectric layer, the first etch stop layer having an opening in a connection area that is located directly above a second portion of the exposed upper surface of the first conductive element; and a second conductive element embedded in a second dielectric layer above the first etch stop layer, the second conductive element being in electrical contact with the first conductive element in a first region of the connection area and in contact with the first etch stop layer in a region outside the connection area.
地址 Crolles FR
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