CHIP PACKAGE FOR HIGH-COUNT CHIP STACKS

摘要

A chip package is described. This chip package includes a substrate having a side at an angle relative to the top and bottom surfaces of the substrate that is between that of a direction parallel to the top and bottom surfaces and that of a direction perpendicular to the top and bottom surfaces (i.e., between 0° and 90°). This side may be configured to couple to a stack of semiconductor dies in which the semiconductor dies are offset from each other in a direction parallel to the top and bottom surfaces so that one side of the stack defines a stepped terrace. For example, the side may include electrical pads. These electrical pads may be coupled to electrical pads on the top surface by through-substrate vias (TSVs) in the substrate. Moreover, the electrical pads on the top surface may be configured to couple to an integrated circuit.

主权项

1. A chip package, comprising:
a substrate having a first surface, a second surface and a side, wherein the first surface and the second surface are substantially parallel, and wherein the side is at an angle relative to a plane of the first surface that is greater than that of a direction parallel to the first surface and less than that of a direction perpendicular to the first surface; first electrical pads disposed on the first surface; second electrical pads disposed on the side; and through-substrate vias (TSVs) electrically coupling the first electrical pads and the second electrical pads, wherein a given TSV electrically couples a given one of the first electrical pads and a given one of the second electrical pads; wherein the second electrical pads are configured to electrically couple to a set of semiconductor dies arranged in a stack in a direction which is substantially perpendicular to the first surface; and wherein the semiconductor dies in the set of semiconductor dies are offset from each other in a horizontal direction in the plane of the first surface so that one side of the stack defines a stepped terrace.