发明名称 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
摘要 A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a p-type nitride semiconductor layer above the second nitride semiconductor layer; two third nitride semiconductor layers of n-type above the second nitride semiconductor layer and located separately on either side of the p-type nitride semiconductor layer; and a first ohmic electrode above one of the two third nitride semiconductor layers and a second ohmic electrode above the other of the two third nitride semiconductor layers; and a gate electrode above the p-type nitride semiconductor layer. The second nitride semiconductor layer includes, in a region above which neither the p-type nitride semiconductor layer nor the two third nitride semiconductor layers is located, a surface layer including p-type impurities identical to those in the p-type nitride semiconductor layer.
申请公布号 US2014225161(A1) 申请公布日期 2014.08.14
申请号 US201414254520 申请日期 2014.04.16
申请人 PANASONIC CORPORATION 发明人 OKITA Hideyuki;UEMOTO Yasuhiro;HIKITA Masahiro;NISHIO Akihiko;TAKEDA Hidenori;SATO Takahiro
分类号 H01L29/78;H01L29/66 主分类号 H01L29/78
代理机构 代理人
主权项 1. A semiconductor device comprising: a substrate; a first nitride semiconductor layer above the substrate; a second nitride semiconductor layer above the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a p-type nitride semiconductor layer above a portion of the second nitride semiconductor layer; two third nitride semiconductor layers of n-type and above the second nitride semiconductor layer, the two third nitride semiconductor layers being located separately on either side of the p-type nitride semiconductor layer; and a first ohmic electrode and a second ohmic electrode, the first ohmic electrode being located above one of the two third nitride semiconductor layers, the second ohmic electrode being located above the other of the two third nitride semiconductor layers; and a gate electrode above the p-type nitride semiconductor layer, wherein the second nitride semiconductor layer includes, in a region above which neither the p-type nitride semiconductor layer nor the two third nitride semiconductor layers is located, a surface layer including a p-type impurity identical to a p-type impurity included in the p-type nitride semiconductor layer.
地址 Osaka JP