发明名称 |
LOGICAL SIMULATION DEVICE, LOGICAL SIMULATION PROGRAM, INTEGRATED CIRCUIT, AND COMPOSITE INTEGRATED CIRCUIT |
摘要 |
<p>PROBLEM TO BE SOLVED: To facilitate design of an integrated circuit which can surely reset a plurality of basic components included in the integrated circuit.SOLUTION: A logical simulation device reads a plurality of basic component macros described as operation models for basic components. The basic component comprises: a plurality of flip-flops 7120 which include reset output terminals for outputting signals indicating whether the basic component is in a reset state or a reset released state; and an output unit 7230 which outputs a reset state signal when the signals output from the respective reset output terminals of the plurality of flip-flops indicate that the basic component is in the reset state. The logical simulation device configures a logical model of an integrated circuit on the basis of a net list and the plurality of basic component macros, executes logical simulation of the integrated circuit by using the logical model, and outputs output data corresponding to input data.</p> |
申请公布号 |
JP2014146108(A) |
申请公布日期 |
2014.08.14 |
申请号 |
JP20130013265 |
申请日期 |
2013.01.28 |
申请人 |
FUJITSU SEMICONDUCTOR LTD |
发明人 |
KOSUGI NAOTO |
分类号 |
G06F1/24;G06F17/50 |
主分类号 |
G06F1/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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