| 发明名称 |
METHOD FOR FABRICATING INTEGRATED CIRCUIT WITH DIFFERENT GATE HEIGHTS AND DIFFERENT MATERIALS |
| 摘要 |
A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing. |
| 申请公布号 |
US2014227844(A1) |
申请公布日期 |
2014.08.14 |
| 申请号 |
US201414255948 |
申请日期 |
2014.04.17 |
| 申请人 |
UNITED MICROELECTRONICS CORPORATION |
发明人 |
LEE Hsiang-Chen;Shih Ping-Chia;Chen Ke-Chi;Wang Chih-Ming;Huang Chi-Cheng |
| 分类号 |
H01L21/8234 |
主分类号 |
H01L21/8234 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for fabricating an integrated circuit, comprising the steps of:
providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing. |
| 地址 |
HSINCHU TW |
