METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

摘要

A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

主权项

1. A method of manufacturing a semiconductor device including:
a memory cell of a non-volatile memory formed in a first region of a semiconductor substrate and a MISFET formed in a second region of the semiconductor substrate, in which the memory cell has a first gate electrode and a second gate electrode adjacent to each other formed over the semiconductor substrate, a first gate insulation film formed between the first gate electrode and the semiconductor substrate, and a second gate insulation film formed between the second gate electrode and the semiconductor substrate and having a charge accumulation portion in the inside, and the MISFET has a third gate electrode formed over the semiconductor substrate and a third gate insulation film formed between the third gate electrode and the semiconductor substrate, the method comprising: (a) providing the semiconductor substrate; (b) forming a first lamination pattern having the first gate electrode and a first cap insulation film over the first gate electrode by way of the first gate insulation film over the semiconductor substrate in the first region, forming the second gate electrode by way of the second gate insulation film, and forming a second lamination pattern having a dummy gate electrode for forming the third gate insulation film by way of the first insulation film and a second cap insulation film over the dummy gate electrode; (c) forming a first side wall insulation film on the side walls of the first gate electrode, the second gate electrode, and the dummy gate electrode; (d) forming, after the step (c), a first semiconductor region used for a source or a drain of the memory cell in the semiconductor substrate at the first region and forming a second semiconductor region for a source or a drain of the MISFET in the second region to the semiconductor substrate by an ion implantation method; (e) forming, after the step (d), a first metal silicide layer over the first semiconductor region for the source or the drain of the memory cell and over the second semiconductor region for the source or the drain of the MISFET; (f) forming, after the step (e), a second insulation film over the semiconductor substrate so as to cover the first lamination pattern, the second gate electrode, the second lamination pattern, and the first side wall insulation film; (g) polishing, after the step (f), the upper surface of the second insulation film to expose the first gate electrode, the second gate electrode, and the dummy gate electrode; (h) removing, after the step (g), the dummy gate electrode; (i) forming, the third gate electrode by filling the first conduction film in a first trench which is a region from which the dummy gate electrode has been removed in the step (h); and (j) forming a second metal silicide layer over the first gate electrode and the second gate electrode, wherein the first side wall insulation film is formed also over the second gate electrode at the step (c), and wherein the first metal silicide layer is not formed over the first gate electrode, the second gate electrode, and the dummy gate electrode at the step (e).