LOCAL INSTRUCTION LOOP BUFFER UTILIZING EXECUTION UNIT REGISTER FILE

摘要

A method and circuit arrangement utilize a register file of an execution unit as a local instruction loop buffer to enable suitable algorithms, such as DSP algorithms, to be fetched and executed directly within the execution unit, and often enabling other logic circuits utilized for other, general purpose workloads to either be powered down or freed up to handle other workloads.

主权项

1. An integrated circuit device, comprising:
a multithreaded general purpose processing unit including a plurality of hardware threads, the multithreaded general purpose processing unit including:
issue logic including an instruction buffer and instruction decode logic, the instruction decode logic associated with a first hardware thread among the plurality of hardware threads;a first, auxiliary execution unit having a register file, wherein a first portion of the register file stores operand data and a second portion of the register file comprises a local instruction loop buffer;a second execution unit; andan L1 data cache; and control logic coupled to the general purpose processing unit and configured to selectively configure the general purpose processing unit to execute a sequence of instructions stored in the local instruction loop buffer, the control logic including:
selection logic interposed between the instruction buffer and the instruction decode logic, the selection logic including a first input coupled to the instruction buffer and a second input coupled to an output of the register file, the selection logic selectable between the first and second inputs in response to the control logic;a software-accessible loop counter that stores a loop count value, wherein the control logic is configured to cause the sequence of instructions stored in the register file to be executed by the auxiliary execution unit a plurality of iterations based upon the loop count value stored in the loop counter; anda software-accessible loop address register that points to a first instruction among the sequence of instructions in the register file, wherein the control logic is configured to branch to the first instruction at the end of the sequence of instructions based upon the loop address register; wherein the instruction decode logic is configured to decode instructions from an instruction set associated with the execution unit, wherein the instruction set includes a first instruction configured to branch into the local instruction loop buffer and a second instruction configured to branch out of the local instruction loop buffer.