TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE

摘要

A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations and generating a mock current to emulate current expected during normal operation.

主权项

1. A device comprising:
a plurality of detection memory cells, each detection memory cell of the plurality of detection memory cells configured to be pre-programmed to a respective initial predetermined state, the initial predetermined state of each of the plurality of detection memory cells configured to be unmodifiable by subsequent commands directed to the memory device; a plurality of reference bits, each reference bit of the plurality of reference bits corresponding to a respective one of the plurality of detection memory cells, wherein the initial predetermined state of each detection memory cell is represented by a corresponding reference bit of the plurality of reference bits; and comparator circuitry coupled to the plurality of detection memory cells and the plurality of reference bits, the comparator circuitry configured to compare a current state of each detection memory cell of the plurality of detection memory cells with a corresponding reference bit of the plurality of reference bits.