发明名称 PROGRAMMING SPLIT GATE BIT CELL
摘要 <p>PROBLEM TO BE SOLVED: To reduce band-to-band carrier generation for memory cells coupled to an unselected row.SOLUTION: In a method of programming a split gate memory, for cells 26 being programmed by being coupled to a selected row and a selected column, a control gate is coupled to a first voltage, a select gate is coupled to a second voltage, and programming is achieved by coupling a drain terminal to a current sink that causes a split gate memory cell to be conductive and coupling a source terminal to a third voltage. Further in the method, for cells 30, 32 not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected, but is sufficiently low, thereby maintaining non-programming state.</p>
申请公布号 JP2014146407(A) 申请公布日期 2014.08.14
申请号 JP20140011512 申请日期 2014.01.24
申请人 FREESCALE SEMICONDUCTOR INC 发明人 HONG CHEONG M;RONALD J SHIZUDEKU;BRIAN A WINSTEAD
分类号 G11C16/02;G11C16/04 主分类号 G11C16/02
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