PHASE-LOCK LOOP

摘要

A phase-lock loop having a reduced lock time in comparison with the conventional art. The phase-lock loop compares an output signal thereof with a reference signal, and alters a control signal in response thereto such that the output signal may have a desired frequency.

主权项

1. A phase-lock loop, comprising:
an input for receiving a reference signal; an oscillator to receive a control signal and to generate an output signal; a frequency divider coupled to receive the output signal of the oscillator and being configured to divide down a frequency of the output signal of the oscillator by a factor, defining a divided down signal; a frequency detector coupled to receive the output signal of the oscillator and to receive a reference signal and configured to generate a comparison signal based on a comparison of frequencies of the reference signal and the output signal of the oscillator; a phase detector coupled to receive the divided down signal and further coupled to receive the reference signal, and configured to generate an output signal based on a comparison of the phases of the divided down signal and the reference signal; a loop filter coupled to receive the comparison signal and to receive the output signal of the phase detector and configured to generate the control signal based upon the comparison signal and the output signal of the phase detector, with the control signal altering the output signal.